1. Field of the Invention
The present invention relates to a semiconductor device and a fabrication method thereof, in particular, to a compound semiconductor device using gold plating and a fabrication method thereof.
2. Description of the Related Art
As the density and integration of semiconductor devices have become high, a multi-layer wiring structure has been widely used. With such a structure, in addition to the accomplishment of high integration, a wiring pattern can be easily designed. However, as drawbacks of the multi-layer wiring structure, the number of fabrication steps increases. In addition, the front surface of a multi-layer wiring structure unsmooths. When the surface of the multi-layer wiring structure unsmooths, a wire breakage and a migration will take place. Thus, the smoothness of the front surface of the multi-layer wiring structure is very important.
The multi-layer wiring structure is obtained as follows: contact holes are formed in a substrate. Metal is clad and patterned. An insulation layer is disposed on the patterned metal. After a predetermined number of layers are formed, bonding pads are formed.
Film materials used for the multi-layer wiring structure are metal films and insulation films. Preferred characteristics of the metal films include a good step coverage, a low resistance, a high ohmic contact to the substrate, a good adhesion to the base material of the insulation film, an easy patterning characteristic, uniform and homogeneous, a high migration resistance, and chemical and thermal stabilities. Preferred characteristics of the insulation films include a good step coverage, an excellent insulation, a good adhesion to metal, a low reactiveness to metal, an excellent passivation against contamination.
Examples of such metal films include Al, Ti, Pt, Mo, W, and alloys thereof. Examples of such insulation films include SiO.sub.2, PSG, SiO.sub.2 --PSG, SiO.sub.2 -plasma Si.sub.3 N.sub.4, Al.sub.2 O.sub.3, and polyimide.
In the multi-layer wiring structure, gold may be plated for a metal so as to decrease the wiring resistance and increase the resultant height. However, the gold plate does not have good adhesion to a CVD passivation film formed thereon. To solve this problem, it is necessary to improve the adhesion to the passivation film by, for example, forming a Ti layer between the gold plate and the passivation film.
Next, with reference to FIGS. 3A to 3H, a fabrication method of a conventional semiconductor device having a multi-layer wiring structure will be described.
A metal film 2 is formed on a GaAs semiconductor substrate 1 (see FIG. 3A). The metal film 2 is composed of an Au layer, a Pt layer, and a Ti layer that successively disposed as an upper layer, a middle layer, and a lower layer, respectively. The thicknesses of the Au layer, the Pt layer, and the Ti layer are 10,000 .ANG., 300 .ANG., and 500 .ANG., respectively. An under-resist 3 is formed on the metal film 2 by photo-etching process (see FIG. 3B). The under-resist 3 is hard-baked (see FIG. 3C). A plating base metal film 4 is formed on the hard-baked under-resist 3. The plating base metal film 4 is composed of an Au layer and a Ti layer that are successively disposed as an upper layer and a lower layer, respectively (see FIG. 3D). The thicknesses of the Au layer and the Ti layer are 1,000 .ANG. and 50 .ANG., respectively. A top-resist 5 is formed by photo-etching process (see FIG. 3E). A gold plate 6 is electrolytically precipitated to an area free of the top-resist 5 for a thickness of 4 .mu.m (see FIG. 3F). The top resist 5 and the under-resist 3 are successively peeled off (see FIG. 3G). A Ti film 8 is evaporated or vapor deposited on the entire front surface of the substrate. The Ti film 8 is photo-etched with a mask. A resist 9 is peeled off (see FIG. 3H). In the above-described steps, the Ti film 8 remains on the plating base metal film 4 in a whisker shape. In addition, it is difficult to form a CVD passivation film or the like on the Ti film 8 in such a manner that the CVD passivation film well covers bulky side walls of the gold plate.
As described above, in the semiconductor device having the multi-layer wiring structure, when gold is plated, a refractory metal such as Ti is evaporated so as to improve the adhesion of gold to the CVD passivation film. However, in this case, it is difficult to well cover the bulky side walls of the gold plate with the CVD passivation film.